Hesham Almatary

That's a good idea and actually, I tried to do so but I wanted to keep the semantic of resetting an extension part of resetting the processor, in case there...

I modified to PR to do a reset when registering an extension. > The thought was that extensions shouldn't need that wide an interface to the simulator. Since it has...

> I'm surprised the extension needed to know the size/location of DRAM; I'd expect the location/extent of data structures to be provided at runtime from the instruction stream. The extension...

> This relates to https://sel4.atlassian.net/browse/RFC-15. I converted this to draft as it doesn't seem ready yet. RFC-15 is mainly about CHERI support, this is just another AArch64 platform without any...

> I think treating Morello as a CPU type is wrong and will lead to problems in the future when there are multiple hardware Morello implementations. So I think there...

> > > This relates to https://sel4.atlassian.net/browse/RFC-15. I converted this to draft as it doesn't seem ready yet. > > > > > > RFC-15 is mainly about CHERI support,...

> > In the Arm world, "Morello" is being interchangeably (and confusingly) used to represent an architecture[extension], an SoC, a CPU, and a board. > > That is highly confusing...

> Any particular reason why using GICv2 instead of GICv3? Two reasons, the first is that I don't think GICv3 is completely properly emulated in QEMU; seL4 hangs on boot...

> > Two reasons, the first is that I don't think GICv3 is completely properly emulated in QEMU; > > I don't see any open bugs related to GICv3 in...

> > > So it seems worth looking into, it may be overly strict. If it works without the `halt()` we can leave it in as a warning, but it...