Hesham Almatary

I believe I've addressed all of the comments on the pending PRs, but please let me know if I have missed any

> CI failure looks unrelated. Change looks good to me now, although you aren't actually using it yet. You can actually build `compiler-rt-builtins-sel4-morello-aarch64` and `compiler-rt-builtins-sel4-riscv64` with this PR. Also if...

> > > CI failure looks unrelated. Change looks good to me now, although you aren't actually using it yet. > > > > > > You can actually build...

> Do you expect this to match the hardware, so we'd put this in a `morello` folder and not `morello-qemu` Not quite. PL011's address and IRQ are different. Also hardware...

> Since this created another PL011 driver, it could be put on top of #157 to reduce the duplication a bit. I believe that's the right direction, but are there...

The rv32imac,gcc failure is likely due to old Binutils installed on the test machines. This could either be fixed by upgrading Binutils there, or maybe use "-z nostart-stop-gc" (as per...

> Err, I may be mixing up the meaning of `(NOLOAD)` in the linker script and the meaning of the `ALLOC` and `LOAD` flags in the section table, and what...

I dropped custom Arm's linker handling for sections and directives and rather added a new commit that unifies the linker script between Arm and RISC-V to include fixes for both...

Also I modified the "retain" attribute to check if the toolchain supports it or not as this may fail on older GCC versions

> Could you rebase this and have a look into the CI issues. Unfortunately, the logs have been deleted, so I can't see why RV32 complains about. Lost track of...