Maximilian Koschay

Emulated substrate ground shortening results in undefined behaviour in other simulators

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The [mgmt_protect_hv.v](https://github.com/efabless/caravel/blob/master/verilog/rtl/mgmt_protect_hv.v) of the Buffer Protection contains a section to emulate the substrate shortening ground together, which was introduced with 4d782844122a8869c6750cdbc1031f5232619b50. ``` assign vssa2 = vssa1; assign vssa1 = vssd;...

Simulator compatibility

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This pull requests contains fixes related to problems with simulation using Modelsim (and probably with other simulators too). # First commit: Most design files of caracel use the Verilog-2001 port...

Net types not explicitly declared, but default_nettyp set to none

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With 08cd6eba30b5b59bbd33a808a9173203d7a7175b and 581068fea64d0d978f060a259cfbb2756bc88e90 the compiler directive ``default_nettype **none**` was introduced to some (not all) files, including all testbench files. The directive requires that the type of nets of all...

Define multible branch prefixes and conventional strategie only

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First of all, thank you for this helpfull tool! In our use-case we want to synchronise a local copy of a customers fairly large git. For this we only want...

I encountered a problem with the reduction of the memory addresses in the uDMA subsystem. I noticed it on the SPI peripheral so I will describe it with this example....