Maximilian Koschay

This is great! Thank you very much! Is there a reason why the resulting files (TLU+, MW files, .db, ...) are not included in the repo? Is it under some...

@RTimothyEdwards I don't think so at all. Like Ronald said, many universities have access to the tools aswell and use it for their work as well as for education. They...

I am struggling to avoid/ fix this issue, when trying to use Mentor Modelsim. Since `default_nettype none` is set, but the port type declarations are still missing, it produces said...

> I can confirm that this works fine with QuestaSim and Xilinx XSim after these changes. > > If dropping default_nettype none is too controversial, I have already started the...

>The Yosys-generated netlists use the non-ANSI style for portlists -- untyped ports, with directions and types (eg wire) specified in the module body. < Direction yes, but not the type....

Hello @it3xl, thank you for your fast response and suggestions. 1. Using multiple sync-projects for the same repository sites. Yes we already thought of this workaround. I guess this would...