hchenji

I get an error when I set LMEM_SIZE in tb_comptue_tile to `LMEM_SIZE = int'(2048*1024*1024);`. When I try to compile it, I get: ``` %Error: ../../../../../../dist/soc/hw/simutil/verilator/inc/../../../../../../dist/soc/hw/sram/verilog/sram_sp_impl_plain.sv:83: Width of bit range is...

optimsoc & synopsys vcs and DC; packet format change to 10 bit src/dst

9

Hi all, great project! I'm trying to use optimsoc in the synopsys toolchain and I'm seeing errors. In VCS I got the errors to go away by replacing the always_ff...

nBanks/nWays error when compiling Gemmini

5

Using chipyard 1.8.0 and gemmini 0.6.4, I get this error when I run build-vcs or build-verilator! ``` [error] /chipyard/generators/chipyard/src/main/scala/config/GemminiSoCConfigs.scala:13:11: parameter 'nWays' is already specified at parameter position 1 [error] Note...

Bluespec 2023.01

1

`make` succeeded, I was able to generate the .bsv from Target.ml. Some of the bluespec includes seem to no longer exist compared to 2014.01. Any hints on what to do?...