Paul Rigge

Some optimizations

4

I got some speedup by doing things in more of a java way. Some of the things I did: - Used array instead of seq - Put value in integer...

Add Dockerfile

2

@ucbjrl, can we set up automatic publishing?

Add Continuous Integration

1

#42 adds a script to test the modules. We should add some CI. @ucbjrl, should we not use travis for new things? What are your thoughts?

freechipsproject/chisel3#679 has an issue about this, I agree with @azidar that it is a good candidate for including in the bootcamp.

Negedge registers can look kind of like posedge registers when doing a full step (posedge + negedge). When verifying behavior with negedge registers, it's nice to be able to half...

[WiP]: Loading verilator as shared libraries

15

This should help with the IPC overhead. Not sure how much of a pain it will be to make this portable. The way it works is this: 1) The verilator...

I think it should probably use `Seq`

Add IntermediateBackend for generating verilog testbenches

2

This is a rough stab at getting the basic functionality to generate a (in my case verilog) testbench via the chisel testers API. The thing I wanted to do was...

Some codegen options are unsupported under multi-proc codegen and it isn't necessarily clear what they should do (e.g. idle output- should each idle output be funneled up? should they all...

With multi-proc codegen (#950) the current system applies the same codegen option to each proc, but you may want each proc to have its own settings (e.g. pipeline depth set...