Paul Rigge

I see this same error with `Verilator 3.922 2018-03-17 rev verilator_3_920-32-gdf3d1a4` on OS X. I used to have an old version pinned that worked, looks like `Verilator 3.900 2017-01-15 rev...

I can't find a reference to merge in our doc. @chick, your instinct matches mine, but I'm still trying to think of why it would be useful.

Sorry for the slow reply. Yeah, you're absolutely correct. `TLMasterModel` has always been a bit rickety compared to AXI, perhaps this is one reason why. I'll assign fixing this to...

Ideally, no wires are needed at all, but Bundles can't get literal bindings if they have bundles inside them. I made a PR last night to try to resume bundle...

Perhaps the type in the DspReal blackboxes should just be Analog. Here is what we did to firrtl to make Analog work with `real` in simulation (warning: it's a hack)....

I think this is resolved by our decision that operations should have their normal behavior (eg typeclass's + === UInt +) and the addition of context_+. I think this issue...

I believe this is related to ucb-bar/chisel3#418 and to an extent ucb-bar/chisel3#417. @ducky64 talked about it at the recent chisel meeting. It's not at all clear to me what the...

Sorry, I fell very behind on my github mentions. I think we agreed to throw an exception for -&

I did investigate this last week and ran into problems. I'll summarize the approaches I played around with. **Zero width wire hack** I thought about having `DspScalar[T

For now, should I add back in a verbose flag to the DspTester?