gongshuaiqi132

xdma: read write fpga user reg abnormal

1

I have a problem CPU and FPGA，PCIE x1 I read and write the FPGA user space reg in the following order： write read write， but the order of the FPGA...

I want to new a heap for a module. To avoid memory fragmentation, when the module is idle, I want to restore the initial state of the heap. How should...