xdma: read write fpga user reg abnormal

[gongshuaiqi]

I have a problem

CPU and FPGA，PCIE x1

I read and write the FPGA user space reg in the following order： write read write，

but the order of the FPGA capture is read write write

I disassembled the CPU code，the order is write read write, ok

why Read/write sequence error ？

thank you very much

[hinxx]

I'm guessing this is from your code and not using reg_rw utility from this repo or similar.

Are doing read()/write() syscalls or mmap()?

FWIW, mmap() always does the right thing for me (did not try read()/write() myself).