Giacomo Travaglini

mem-ruby, configs: Add a generic CHI controller as a stepping stone for ruby+classic topology

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This PR is mainly adding a CHIGenericController class to model a coherence controller entirely in C++ to work with ruby. This is a stepping stone towards supporting a hybrid setup...

**Describe the bug** As reported in one of the gem5 slack channels (https://gem5-workspace.slack.com/archives/C03K26BGTKL/p1703584762742109) the queued prefetcher translates request with the BaseMMU::Read argument [1]. This automatically informs the MMU to look...

base, mem-cache: Make the AssociativeCache more generic

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This PR implements #1429. It mainly achieve so with the following changes 1) The IndexingPolicy is now a templated SimObject to make its APIs work with different data types. As...

**Generic Cache library** The AssociativeCache introduced in https://github.com/gem5/gem5/pull/745 models a base associative storage managed by our existing indexing and replacement policies. At the moment the AssociativeCache is mainly used by...

arch-arm: Add support of AArch32 VCVTA/P/N/M instructions.

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Add decoder and function of AArch32 VCVTA, VCVTP, VCVTN and VCVTM instructions. Support both 16-bit and 32-bit variants. Only support A32 encoding. Change-Id: I6ece0e1b779f9a7cc9d709894a49a7fdcda28373 Reviewed-by: Giacomo Travaglini

With https://github.com/gem5/gem5/pull/1446 we are unpacking the KeyType into the Addr tag and in the secure bit. We should in the future store the KeyType directly. This not only makes the...

Handle secure/non-secure address space in prefetcher code

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The refactoring of the generic cache in https://github.com/gem5/gem5/pull/1446 exposed an existing problem in our prefetcher code: while most of them seem to be using the TaggedEntry (which is a cache...