Giacomo Travaglini
Giacomo Travaglini
Hi @arichardson. Software prefetching has a hacky implementation in gem5 which makes it buggy in some cases. I have already seen several PRs trying to put a patch on a...
I need to look at this more carefully. An initial solution (a bit of a hack), would be to handle squashing due to faulting differently from simple re-execution (in the...
This is a weird issue to happen on a in-order CPU. Is it possible this is a just RISCV issue (eg the instruction wrongly mislabelled) ? I am looking at...
Hi @robhau > Hi, thank you for your comment 😄. > > > Is it possible this is a just RISCV issue (eg the instruction wrongly mislabelled) ? > >...
> Could the branch target predictor be the problem? > > The branch predictor predicts taken, because it is an unconditional branch. > > https://github.com/gem5/gem5/blob/3b7307182f272756bd805ca2d5f4af79efa639a0/src/cpu/pred/bpred_unit.cc#L120-L163 > > After that, the...
> Would you be willing to talk about this in the next gem5-dev meeting? Will it be on the 9th of May? If that's the case I won't be able...
Hi @BobbyRBruce, I have some time this week to dedicate at this PR. Do you mind if I steal it from you? It would be nice if we could get...
> The PR isn't on the ToT of develop branch, can we rebase it? I just rebased it
> Cool! We are doing something similar: see gem5 issue #1164. > Yes I saw the issue few days ago and I also noticed the similarity > I notice that...