myrtle

*PKREG* bits mirrored

1

See https://github.com/gatecat/nextpnr/commit/6fc050a622e05bd9b484e4302d0ca0199e39a1fb `TPKREG1`, for example, actually seems to configure `FFT0`. I'm not sure if this is bad naming from Quartus or something Mistral has control over.

Fix some compile warnings and errors on an up-to-date system

8

This enables OpenROAD to build with a recent compiler; without hitting warnings that become errors due to -Werror (the first commit, the `free` on a class member, is a particularly...

The documentation for the units in the https://github.com/SymbiFlow/prjxray/blob/cb5f2a30633bf0d3ac91a9b5802790ac1da86736/docs/dev_database/common/tile_type.rst#pips-section doesn't seem to be correct. Not only does it mention `us (nanoseconds)` which must be a typo, it doesn't seem to be...

PDN short circuiting Metal1 in endcap/tbtie cells

9

### Description We are using OpenROAD (with ORFS) to tape out on a proprietary PDK. The cell library contains endcap, corner and tbtie cells that contain a metal1 ring (that...

Adding nextpnr routing timing support

3

This currently imports a simplified set of routing delays to nextpnr. Remaining TODOs: - [x] site input timing - [ ] populating the cell pin timing structures

Consider trying to patch the exception map, for example to test SymbiFlow/fpga-interchange-schema#42. Aside from the `StringIdx` issue in #81, patching something that is a list rather than a struct fails...

At the moment, patching of `StringIdx` values fails. Consider the following example: parameters.yaml: ``` cells: - cellType: FOO ``` running ``` python -mfpga_interchange.patch --schema_dir ~/fpga-interchange-schema/interchange --patch_path parameterDefs --schema device --patch_format...

Cleaner nextpnr BBA generation

2

Currently the nextpnr BBA generation code includes a lot of duplication, particularly where lists are concerned. e.g. patterns like https://github.com/SymbiFlow/python-fpga-interchange/blob/6a80233ca97427c9b1a1cdd16349c3724914d008/fpga_interchange/chip_info.py#L658-L672 crop up a lot I think a custom decorator might...

Requiring a NULL tile at (0, 0) is Xilinx-specific

5

https://github.com/SymbiFlow/python-fpga-interchange/blob/master/fpga_interchange/populate_chip_info.py#L1139 assumes that the tile at (0, 0) is NULL. This works for Xilinx, and can be made to work for Nexus by renaming that tile (because it's equivalent to...