myrtle
Based on some recent comments in YosysHQ/yosys#2567 it is apparent that negative bus indices are legal Verilog (and occasionally used for the fractional part of fixed point values) and therefore...
Hi! We are trying to use `comment-progress` to provide docs preview URLs in pull requests. However, when that PR comes from another repo where the submitter doesn't have permissions, it...
Prerequisites: - [ ] wire types, as being discussed in SymbiFlow/fpga-interchange-schema#31 - [ ] specification for more complex rules, SymbiFlow/fpga-interchange-schema#34 Global clock routing is likely to be based on a...
The rules to prevent duplicate or leading/trailing underscores make sense when other characters are being translated to underscores, but in my opinion make less sense when underscores are present in...
Yosys supports several non-standard features of the BLIF specification that bring it more up to speed with a modern netlist format. Some other FPGA consumers of the BLIF format use...
### Describe the bug This line in odb: https://github.com/The-OpenROAD-Project/OpenROAD/blob/6231dc8c45d6eee2b5dd64aa32279820a26ab0e6/src/odb/src/db/dbTable.hpp#L252 assumes that a placement new keeps uninitialised fields, like `_oid`, intact. But this isn't the case, and indeed with a new...
This follows the alternative approach described in https://github.com/The-OpenROAD-Project/OpenROAD/pull/5349#issuecomment-2223108708, with a new option to stop at the extent of the power pins of endcaps. This prevents the power stripes extending further...