Garrin Kimmell

I want to be able to generate asynchronous resets, which in VHDL would look like: process foo(clk,rst) is begin if (rst = '1') then blah elsif rising_edge(clk) then blah end...

Add Case Expression

2

Something like: ExprCase Expr [(Expr,Expr)](Maybe Expr)

signal f_sel : std_logic_vector(1 downto 0); f_sel(0)