libriscv
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fwsGonzo
C++20 RISC-V RV32/64/128 userspace emulator library
The binary translator needs to be activated before fastsim is realized, so that we can pretend that binary translation blocks are JAL instructions - so that fastsim does not skip...
At some point I will make a prototype bytecode simulator that replaces the current decoder cache method. Instead of function pointers, I will create more easily decoded instructions using the...
Right now the translator tries to find interesting blocks that it thinks will work well with binary translation, and only translates those. It would probably be better to just translate...
It is possible to make compressed instructions faster using fastsim because it stores instructions separately as 32-bit. This will improve C-extension performance, but it will still not be able to...
This will require some quirk-fixing of many thread system calls and the slow paths
The STREAM benchmark compiled with GCC 10 and compressed instructions hits a FUTEX deadlock. ``` >>> Machine exception 10: FUTEX deadlock (data: 0xB78E5D8) -> [0] 0x000000000001AF10 + 0x024: __lll_lock_wait_private ->...
I have just laid the foundation down to hopefully be able to implement supervisor mode, at some point. By adding a cacheable flag to pages, we can have an uncacheable...
On Windows, many of the basic system calls are stubbed and it's not guaranteed that even basic programs will run there. This needs to be fixed.
# Usecase I want to from the Windows operating system load a RISVC compiled shared library. The use case is load a shared library that provides three symbols. There are...
It'll be helpful to standardize on the author's coding style for consistency.