chisel-testers

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Add IntermediateBackend for generating verilog testbenches

2

This is a rough stab at getting the basic functionality to generate a (in my case verilog) testbench via the chisel testers API. The thing I wanted to do was...

grebe

verilator DUT cpp generation bug

1

Running a Verilator test twice doesn't reproduce the DUT cpp code. This can be seen by first generating a DUT with a Vec IO of some size, and then generating...

stevobailey

VCS Help

1

@jcmartin @donggyukim anyone else -- have you guys run PeekPokeTester w/ the VCS backend? I'm getting a ``` ../vpi.h: In member function 'virtual void vpi_api_t::tick()': ../vpi.h:26: error: 'template class sim_api_t'...

shunshou

I thought it was via testCmd = Seq(), but it's not doing anything for me???

shunshou

Supposedly you can specify a file location, but seems like the VCD is just dumped into the test_run_dir/YourProjectHere directory...

shunshou

Verilator fails on lines like this in generated verilog: $fwrite(32'h80000002,"output test event %d testing mem_out.bits = %d, should be %d\n",_T_12,device_under_test_io_mem_out_bits,_GEN_7); when device_under_test_io_mem_out_bits width is larger than 64 bits with this...

aayupov

If, in certain conditions, it's not allowed, I wouldn't mind having Verilator fail... but otherwise, even if an inout port (of a blackbox) is actually just the sume of two...

shunshou

The code seems to just ignore the second argument to assert.

jcmartin

Post-synthesis simulation

22

The basic issue is that I need to do synthesis post-simulation. The old way of doing this was to generate the harness from chisel, use VCS to compile it with...

jcmartin

PeekPokeTester catches TestApplicationException, returning failure if the exit code is non-zero. Some simulations (notably vcs) do not set a reliable exit code, but in any case, we should signal up-level...

ucbjrl