Should the verilator backend let you peek/poke an analogType?

[shunshou]

If, in certain conditions, it's not allowed, I wouldn't mind having Verilator fail... but otherwise, even if an inout port (of a blackbox) is actually just the sume of two inputs, I can't actually probe that it's right. Basically, I want to sanity check that connections are made correctly, and I can't do that in simulation.