FPGA_PSYC

I tried using the Intel Triple Speed Ethernet Ip but it only provides option for LVDS Serdes and not for GX bank. Can you help me how i can integrate...

Hi Alex, Waiting for your valuable suggestion on this. Please help me with the design generation.

i Would like to build

Yes. There is a byte missing. The output is from the udp core. When the tready is low, the data has to be stored in a temp buffer and then...

Dear alex, The issue is not yet fixed. Please note the attached image, you can see that store_udp_payload_axis_temp_to_output is not high due to which we are having a byte loss....

Its a Simulation trace. I am using xilinx gigabit ethernet ip. That ip is generating the required axis clock which i am feeding to stack. In Ip_rx its working as...

I am using a example design of vcu118 where the udp packet is being looped back. I even tried tieing the ready pin with 1. The same issue occured.

No. The loopback logic which checks for the udp source port and loopsback using the fifo is taken without any modifications. I have put them in the top file where...

The ip_rx module also have the same logic similar to the udp_rx except for the header decoding logic. The ip_rx is working good but udp_rx didnt. I am not sure...

No, there is no change. still tready_reg does not go low after the tready_next goes low.