fontamsoc

symbiflow_place exit with code 1

1

https://lists.librecores.org/pipermail/symbiflow/2021-December/000059.html I am attempting to build [FonTamSOC](https://github.com/fontamsoc) targeting NexysA7. `symbiflow_place` exit with code 1 Find full logs at: https://drive.google.com/file/d/13_29bNH2x3Fo68F_nOYL5NlFapP5S7ZQ/view?usp=sharing Steps to reproduce failure: ``` # clone verilog sources: git clone...

ERROR: Incorrect period value

4

https://lists.librecores.org/pipermail/symbiflow/2021-December/000049.html Hello, I am attempting to build [FonTamSOC](https://github.com/fontamsoc) targeting NexysA7. However, `symbiflow_synth` fails with `ERROR: Incorrect period value` at the end of the logs. Steps to reproduce failure: ``` #...

Is it possible to adjust burst-length in order to widen data path ? Specifically, I would like to widen the data port of the DDR2 controller used with NexysA7 (aka...

I am successfully using litedram_core on OrangeCrab02-25F when user_ports is wishbone, however when user_ports is native, liblitedram fails to initialize the controller through its wb_ctrl ports. Here is litedram_core generated...

porting tinycc

1

I am looking to port tinycc to the PU32 instruction set described at: https://github.com/fontamsoc/docs/blob/master/isa.md https://github.com/fontamsoc/docs/blob/master/isa-sys.md PU32 uses following ABI: https://github.com/fontamsoc/docs/blob/master/abi.md How to describe the ABI when porting tinycc ?

In my LiteDram yaml file, I am using Wishbone user port as follow: ``` "user_ports": { "wishbone_0" : { "type": "wishbone", }, }, ``` The generated Wishbone port does not...