Results 812 comments of Andre Weissflog

I have a complete rewrite of the resource update functions in mind that would basically look like the WebGPU update functions (e.g. write from CPU to GPU memory, copy between...

Hmm interesting, I thought that the ZX doesn't have special logic to place an interrupt vector on the data bus when an IM2 interrupt happens, but instead it takes whatever...

...in the schematics, the CPU M1 pin doesn't seem to be connected to anything else: ...so there's two scenarios to figure out (since M1 is out of the race): -...

PS, the 'fallthrough' fix would look like this: ```c if ((pins & (Z80_A0|Z80_RD)) == Z80_RD) { // read from ULA ... } else if (if ((pins & (Z80_A0|Z80_WR)) == Z80_WR)...

Hmm yeah, the actual PR diff looks scary and has a lot of unrelated changes. I will probably integrate your tick function changes manually. PS: I've converted the PR to...

Hmm, we should confirm those findings against the netlist simulation: https://floooh.github.io/visualz80remix/ I had looked at those instructions here: https://floooh.github.io/2021/12/06/z80-instruction-timing.html, but didn't pay particular attention to the flag bits. ...still strange...

Btw, many thanks for listing all this information here, it's a great reference.

Man, @hoglet67 really is *the* Z80 master mind, he also figured out what was wrong with the netlist simulation code in https://github.com/floooh/v6502r (https://stardot.org.uk/forums/viewtopic.php?p=349760#p349760).

Yeah, Oryol is totally outdated and abandondend. I'll need to update the fips documentation to use a different sample project (fips itself *is* actively supported though, I use it everyday,...