Flavien Solt
Flavien Solt
Some fixes in the debug_rom/gen_rom.py script. Importantly, map has no len, therefore it seems necessary to cast it to a list and this script does not run as it was,...
Hi there! I've detected a bug in VexRiscv. ## Brief bug description Some sign injection instructions, such as `fsgnj.d` or `fsgnjx.d`, behave incorrectly when encountering NaNs. ## Example instance ###...
Hi there! I stumbled into a segfault in Verilator (with `Verilator 5.021 devel rev v5.020-31-g54922c036`). ```bash Thread 1 "Vtop" received signal SIGSEGV, Segmentation fault. trace_init (voidSelf=0x5555555b1740, tracep=0x5555555d7958, code=1) at Vtop.cpp:117...
Hi there! I found a double bug for Verilator on the same design. - The VCD trace is corrupted - The value is wrong, even if traces are enabled. Note...
Hi there! # Summary I found a bug where Verilator produces a wrong simulation result in a circuit made of XOR gates and adders. One output bit is erroneous (`out_data[160]`...
Hi there! In some hard-to-reproduce cases, some malloc assertion fails. ``` Vtop: malloc.c:2379: sysmalloc: Assertion `(old_top == initial_top (av) && old_size == 0) || ((unsigned long) (old_size) >= MINSIZE &&...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description I create a new issue, similar to #1071, but...
Hi there! I discovered a little bug in BOOM. The riscv 1.12 privileged spec states: > Any CSR write takes effect after the writing instruction has otherwise completed. However, this...
Hi there! fsqrt was known to produce [some off-by-one errors](https://github.com/openhwgroup/cvfpu/issues/68), and may return 1 on canonical NaN. This snippet shows that additionally to these known problems, `fsqrt.s` can return large...
Hi there! ### Overview While [this issue](https://github.com/openhwgroup/cvfpu/issues/68) showed that fdiv can return a result off by one and therefore return NaN instead of infinity, I found that `fdiv.s` may return...