prjuray
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f4pga
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
Looks like half the work is done: https://github.com/SymbiFlow/prjuray/blob/3f5736237309e0670b4351f39fad8b4bd9cb6dd0/tools/dump_features.tcl#L646 but this isn't actually appearing in the databases yet presumably because nothing actually fuzzes this. I believe this is needed to correctly...
Bitstreams from Vivado are failing the ECC check in bitread. This likely indicates there is something about the ECC calculation that is misunderstood. For now, ECC checking has been disabled....
I, and I suspect quite a few others out there too, am currently using a zcu104 for UltraScale+ testing which is 7ev based. This board was one of the easiest...
Being able to build litedram through this would be a medium-term target for me, as I already had it working with the nextpnr+RapidWright flow (subject to bitrot, it may still...
Looks like the 1/2/4/9/18 bit BRAM width options are missing in the database. I can only see bits to enable the 36/72 bit SDP modes.
I've seen a couple different forms of instability in the IOB fuzzer results. Examples: Transpose of LVCMOS18 I6 I8: ``` -HPIO_RIGHT.IOB_X0Y12.IOSTANDARD_OUT.LVCMOS15_IDRIVE_I6_SLEW_SLEW_FAST_LVCMOS18_IDRIVE_I6_SLEW_SLEW_FAST_LVCMOS18_IDRIVE_I8_SLEW_SLEW_FAST !02_689 !02_703 !02_745 !02_746 02_778 03_688 !03_693 !03_696 !03_700...
CMT_RIGHT contains the PLL and MMCM blocks, along with the BUFGCTRL and BUFGCE_DIV blocks. CMT_RIGHT's interconnect is fairly complicated, so a more focused fuzzer is likely required to document those...