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Published 20 hours ago • verified publisher icon f4pga

HPIO config settings needed for litedram

Open daveshah1 opened this issue 4 years ago • 0 comments

Being able to build litedram through this would be a medium-term target for me, as I already had it working with the nextpnr+RapidWright flow (subject to bitrot, it may still even be working).

This will require the following extra HPIO modes/options to be fuzzed:

  • DIFF_POD12_DCI input/output (DQS), DIFF_SSTL12_DCI output (DRAM clock)
  • PRE_EMPHASIS
  • EQUALIZATION
  • INTERNAL_VREF

Reference: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/zcu104.py and https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/mercury_xu5.py

daveshah1 avatar Jul 19 '20 10:07 daveshah1