evanshultz

The package drawing looks perfect to me, but it's not from TI. I'd rather have the full datasheet from an "official" URL than a package drawing from a 3rd party...

KLC doesn't specify silk offset from fab lines, but our informal standard and scripted value is 0.11mm. This means a 0.1mm fab line just touches a 0.12mm silk line. Granted,...

@LJJS Sorry for the long delay. Are you still here? https://github.com/KiCad/kicad-footprints/issues/955#issuecomment-691848591 finally gives us direction on how to name this footprint, so if you can rename and make any other...

That is not a valid footprint name for this library. See our footprint naming scheme at https://kicad-pcb.org/libraries/klc/F3.6/. And these check scripts are for those guidelines/rules. So as @cpresser said, this...

I think you will get more responses if you post this question at https://forum.kicad.info/. That forum is for KiCad users.

I suggest to start with robust checking, refine that as needed, and then make courtyard creation a second step. That brings some benefit more quickly and allows discussion about how...

I'm not that familiar with the symbol generator, but just looking at the symbol above I don't have any reservations. This looks like an incredible contribution!

@ObKo Because there are so many things that could vary, let's only allow Xilinx-specific footprints. So use a single footprint filter like `Xilinx*CPG238`. The footprints are duplicated for the +1...

This clearance is specified at http://kicad-pcb.org/libraries/klc/F5.1/. While KLC mentions 0.2mm of clearance, recent IPC 7351 docs say the line width (for us it's 0.12mm) is acceptable and in fact we...

@poeschlr Do you still want to revisit this? If so, we'll need to merge in master in order to merge this PR.