evanshultz

Page 24 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/en5319qi_08325.pdf shows 0.2mm vias with 0.6mm pads. Since we often use 0.3mm holes in the library I would accept 0.3mm vias with 0.6mm annular rings, which will...

1. Can you list PNs, wildcarded or not, that can use this footprint in the description? That will help users to search for this footprint in the future, I believe....

The generator should place the vias relative to the thermal pad size, if possible, so changing the drill size should only slightly shift the via positions. Probably not a big...

That could be done. Is there some relationship you are thinking about for drill size and EP size? If the min drill size is in KLC then it could be...

I see. Yeah, I don't quite think KiCad supports that situation well. One standard size of thermal via drill in all EPs seems suitable for now, to me. Gotcha. So...

Hello @tpimh . Is this a request for footprints? If so, our chip footprints are generated by a script at https://github.com/pointhi/kicad-footprint-generator/tree/master/scripts/SMD_chip_package_rlc-etc.

Symbols have been merged.

I was going back to old PRs trying to clean them up and found this. A few issues remain: 1. Beef up the description so it's more than just a...

- Remove the `-1EP` section because this footprint now doesn't have an exposed pad. This also applies to the symbol using this footprint. - Can you add the slug dimensions...

I assume this was created by hand. Would you be willing to script it? I believe the script at https://github.com/pointhi/kicad-footprint-generator/tree/master/scripts/Inductor_SMD will work.