Edward Shogulin

### Details: - *[CPU] [AARCH64] jit sigmoid* ### Tickets: - *CVS-132534*

### Details: - *[CPU] [AARCH64] jit eltwise: infrastructure + some ops + Relu* ### Tickets: - *CVS-128641*

Advanced SIMD: not covered instructions

1

Hi guys, Some instructions from here https://developer.arm.com/documentation/ddi0597/2023-12/SIMD-FP-Instructions?lang=en are absent in https://github.com/fujitsu/xbyak_aarch64/blob/main/src/xbyak_aarch64_mnemonic.h. For example: VLDn (1..4), VMAX, VMIN... and many other. Am I looking in the wrong place or is it...

### Details: - *Exception handling: exception message logging* ### Tickets: - *NotSupported exception can have message, let's display it. For example this ticket will be clear in this case: CVS-139934*

### Details: - *[CPU] [ARM] JIT Elu* ### Tickets: - *CVS-139593*

### Details: - *[CPU] [ARM] JIT Mish* ### Tickets: - *CVS-139718*

[CPU] [ARM] JIT GELU Erf

1

### Details: - *[CPU] [AARCH64] jit gelu erf* ### Tickets: - *CVS-138192*

[CPU] [ARM] JIT GELU Tanh

1

### Details: - *[CPU] [ARM] jit gelu tanh* ### Tickets: - *CVS-138293*

[Good First Issue] [ARM]: Implement CPU plugin just-in-time emitter for IsInf operation

3

### Context [JIT Emitters](https://github.com/openvinotoolkit/openvino/blob/42f1cb095143f19c0b9ee25836c29748bc8d9bf2/src/plugins/intel_cpu/src/emitters/README.md) are part of code generation feature (a.k.a. tensor compiler) that automatically produces highly-efficient optimized fused subgraph binary code. Each emitter implements specific operation from low level...

[Good First Issue] [ARM]: Implement CPU plugin just-in-time emitter for GreaterEqual operation

2

### Context [JIT Emitters](https://github.com/openvinotoolkit/openvino/blob/42f1cb095143f19c0b9ee25836c29748bc8d9bf2/src/plugins/intel_cpu/src/emitters/README.md) are part of code generation feature (a.k.a. tensor compiler) that automatically produces highly-efficient optimized fused subgraph binary code. Each emitter implements specific operation from low level...