Lee Moore

returning to this issue, I have run the testcase on the 0.8.0 PR https://github.com/openhwgroup/core-v-verif/pull/1599 I have pending make test TEST=debug_priv_test CFG=pmp The result is as follows firstly it tries to...

try running with the flags --help or --helpall there are a number of trace options, for example, I would recommend first selecting --trace --tracechange but there are many other trace...

Hmm, I will double check but I think it gets stuck in a loop soon afterwards E.

@aswaterman You were correct, but a later exception gets stuck into a loop core 0: 0x00000000800000bc (0x00000073) ecall core 0: exception trap_machine_ecall, epc 0x00000000800000bc This goes back to the trap_vector,...

@aswaterman Hi Andrew, maybe I am asking the wrong question :-/ I am trying to run the suite of verification tests from https://github.com/riscv/riscv-tests I think I should use spike, as...

As I recall, the handler WAS called, it so happens the handler address is set to the next instruction after the exception address, so it appears to continue running

@silabs-hfegran Can you give a little more detail on how to reproduce, previously I would do the following export CV_CORE=cv32e40x pushd core-v-verif/${CV_CORE}/sim/uvmt make test TEST=clic CFG=clic_default CV_CORE=cv32e40x USE_ISS=1 RNDSEED=0 popd...

Hi Henrik, the manual says this core does not support user mode Can you clarify The specification says: *To accelerate interrupt handling with multiple privilege modes, a new CSR xscratchcsw...

> mscratchcsw is listed in the 'CLIC CSRs' section of 'smclic M-mode CLIC extension' and its behavior seems well defined also for CPUs with only machine mode. Hi @Silabs-ArjanB The...

@Silabs-ArjanB We interpret this differently, can I refer you to the following https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc#4710-scratch-swap-csr-xscratchcsw-for-multiple-privilege-modes 1. The title of the section for the csr xscratchcsw says > 4.7.10. Scratch Swap CSR (xscratchcsw)...