Lee Moore

@strichmo @Silabs-ArjanB @silabs-oysteink I am hoping someone can direct me. Following the steps to reproduce I have an issue with this command > % makecv32 comp_corev-dv gen_corev-dv test TEST=corev_rand_debug SEED=1...

I think this was a complete typo, I removed the 'makecv32' and replaced with just 'make' I think this was the issue. I am now seeing the SHELL interpreter issue...

@silabs-oysteink aha, we overlapped - I will go back and undo what I did - thx

Hi All well this is disconcerting - for me it passes ? This would indicate a difference in the simulator event propagation How do I now pass options to the...

@silabs-oysteink @strichmo @Silabs-ArjanB Hi All I need a trace file from a failing simulation, as I have mentioned, mine does not fail. I am running xcelium version > xrun -version...

This is the log I have from running the make command line (this has full tracing enabled) [simulate.log](https://github.com/openhwgroup/cv32e40p/files/5401548/simulate.log) This is generated by adding in the following parameters to the ISS...

Update, reproduced the issue and investigating .... Looks (at first glance) as though #548 is the same issue

Hi All having made a change to the RM in order to ensure correct handling of dret in Machine mode during single step, we see unexpected behavior earlier in the...

update it would appear that the problem we are seeing is possibly due to the setting of the haltreq signal too early at the ISS @silabs-oysteink and myself are still...

still open, I have not had time to investigate a good way to schedule the haltreq signal, I will get some time today to re-investigate