Lee Moore

still open, I have not had time to investigate a good way to schedule the haltreq signal, I will get some time today to re-investigate

I can reproduce this issue running cv_regress with the ImperasDV flow, I am not sure why your (current) testbench does not flag this as an error

@silabs-hfegran This is documented here for all of the possible bespoke configurations Imperas/doc/ovp/OVP_RISCV_Model_Custom_Extension_Guide.pdf Can you take a look at the section on CLIC, and let me know what your configuration...

I tried to reproduce this issue in the following way (first running the sanity test) git clone https://github.com/silabs-anvesten/core-v-verif cd core-v-verif git checkout c8ed2ef make clean_all make sanity CV_CORE=cv32e40x But I...

Looks like an error in this file ./cv32e40x/tb/uvmt/uvmt_cv32e40x_iss_wrap.sv: CPU #(.ID(ID), .VARIANT("**CV32E40X_V0.0.0**")) cpu(bus, io);

I also tried git checkout DebugBug make test TEST=debug_priv_test CFG=pmp And I got a different error > make test TEST=debug_priv_test CFG=pmp > CRITICAL:yaml2make:Could not find [test.yaml] in any directories: >...

I can see the issue here, there is some common code in the model between the E40P, E40X and E40S this field is defined in the online docs as follows...

Having now cleared the backlog of work with Marton (non specified behavior for NMI) in the legacy testbench/model - I am now starting to look at these other issues. As...

@Silabs-ArjanB for the issue mentioned here > mret in debug mode increments minstret (https://github.com/openhwgroup/cv32e40x/issues/558). Which cores does this apply to E40P, E40X, E40S and also which version - is this...

(0.2.0) Bitmanip enable-overrides appears to not function correctly (e.g. ctz triggers illegal instruction when enabled) can you please tell me how to reproduce this issue