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bilalahmed-RS

Axi_lite_to_wishbone: Reduce latency, make latency configurable

12

- First commit reduces the latency for the request handover by 1 - Second commit reduces the latency for the rw data handover by 1 Benchmark with NaxRiscv (this uses...

cklarhorst

This PR adds retransmissions to the Etherbone host code. Instead of immediately throwing `socket.timeout` exception the modified code retries the request up to 10 times within the specified timeout period....

mkurc-ant

Fixes a couple minor issues with the bare metal software demo encountered under Nix. 1. Programs are stored without write permissions. The demo data copied to the build directory is...

tpwrules

Increase JTAG UART upload speed

1

This patch increases the JTAG UART upload speed by switching to nonblocking read mode in the OpenOCD Tcl script, then reading and writing up to 512 byte blocks instead of...

tpwrules

I did not find a way in the build process to automatically add additional commands & special init code to the bios. Example Workflow: `pip install pythondata-module-can` A target with:...

cklarhorst

I have been trying to use litepcie for building some of my SoCs. I have installed python, icarus verilog (instead of verilator) and have also followed all the steps given...

anandsime

According to rfc2347, responses to OACK should be ACK in read, and DATA in write. ``` Read Request client server ------------------------------------------------------- |1|foofile|0|octet|0|blksize|0|1432|0| --> RRQ ACK ACK ACK RRQ DATA DATA

hashhsah

litepcie driver creation result in error if I create board without build parameter

1

thanks in advance in last version you have used vns_exit = builder.build(**vivado_build_argdict(args), run=args.build) but now if args.build: builder.build() if args.driver: generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) as a result if I try to...

1n3o1

axi stream buffer

2

thanks in advance should not you buffer in axi stream be like this class Buffer(Module): """Pipe ready and valid and all data to cut timing path""" def __init__(self, layout): self.sink...

1n3o1