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Small footprint and configurable DRAM core

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This has been initially mentioned in https://github.com/enjoy-digital/litedram/pull/173. When writing tests for `core.multiplexer._CommandChooser` I've noticed that the request selection defined here: https://github.com/enjoy-digital/litedram/blob/b06e946d09807f3ab9b2e72f9c599851ab8221b4/litedram/core/multiplexer.py#L42-L47 seems to work wrong in some cases, e.g. *...

needs-review

In `_LiteDRAMBISTGenerator` the `base` address is being aligned to `dram_port.data_width` and `length` denotes the number of commands issued (https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/bist.py#L187). In `_LiteDRAMPatternGenerator` the address passed in `init` is not being shifted....

enhancement

WIth current `_LiteDRAMBISTGenerator` and `_LiteDRAMBISTChecker` we can already test linear addressing or full random addressing (based on a LFSR). This will allow producing the first bandwidth/efficiency results for the different...

enhancement

Currently, each bank has its own bank machine. On designs where efficiency is less critical, being able to reduce the number of bank machines and sharing a bank machine between...

enhancement
help-wanted

Ports can now expose banks to user and can allow reordering accesses to the memory. To implement reordering, we could create a module that would work on two native ports:...

enhancement
help-wanted

To support higher frequencies in dual/quad rank mode, we will need to drive ODT dynamically. Useful information can be found in: - TN-41-08: Design Guide for Two DDR3-1066 UDIMM Systems...

enhancement
help-wanted

I had the following issue with current master in MiSTeX: The sdram usually initializes correctly, and often ran well for up to ten minutes or so, but then the Screen...

Trying to get LPDDR working on a Cyclone IV board. Is there a way to quickly change GENSDRPHY into GENDDRPHY?

This fixes multiple instances of: litedram/phy/lpddr4/commands.py:209 litedram-2023.12/litedram/phy/lpddr4/commands.py:209: DeprecationWarning: invalid escape sequence '\d' "BA(\d+)": lambda i: self.dfi.bank[i],

Hi All, I am trying to bring up DDR4 on htg-940 board using litedram (I managed to get the spd dump over I2C). I feel like I have made some...