Benchmark: Allow testing complex/pre-defined access patterns

[enjoy-digital]

WIth current _LiteDRAMBISTGenerator and _LiteDRAMBISTChecker we can already test linear addressing or full random addressing (based on a LFSR). This will allow producing the first bandwidth/efficiency results for the different configurations, but we will probably need to test more specific access patterns when LiteDRAM is used for specific applications where access pattern is known in advance and we want to be sure to maximize performance. We should create a new gateware modules that are executing the access passed in the init parameters and with following prototypes:

address_data_pattern = [
    # address    data
    (0x00000001, 0x12345678),
    (0x00000010, 0xdeadbeef),
]

@ResetInserter()
class _LiteDRAMPatternGenerator(Module):
    def __init__(self, dram_port, init=[]):
        self.start  = Signal()
        self.done   = Signal()
        self.ticks  = Signal(32)

        # # #
[...]

@ResetInserter()
class _LiteDRAMPatternChecker(Module):
    def __init__(self, dram_port, init=[]):
        self.start  = Signal()
        self.done   = Signal()
        self.ticks  = Signal(32)

        # # #

[...]

pattern_generator = _LiteDRAMPatternGenerator(self.sdram.crossbar.get_port(), init=address_data_pattern)
pattern_checker   = _LiteDRAMCheckerGenerator(self.sdram.crossbar.get_port(), init=address_data_pattern)

And integrate them in the benchmark. We should be able to pass the address/data pattern from the command line: --pattern-init=...

Theses modules could be located in frontend/bist.py.