Kevin Laeufer

> Looks okay to me. Still work in progress. So far I only undid your changes...

> I'd be happy to talk to you more about this if you'd like Sounds good. I mostly want to have a more expressive waveform view. Let's consider this a...

> I wrote a specification for FST [here](https://blog.timhutt.co.uk/fst_spec/). Thanks for writing that spec Tim! I actually had a look at it when I was implementing the FST reader for Surfer....

I think the problem is the implementation of `findTopLevelClocks`. The function should ideally only consider input **ports**. Currently it considers a lot of derived clock signals to be independent clocks.

Here is an example where you would expect the output to always be `123` and never `0`: https://scastie.scala-lang.org/TlYbM54hSLOShAxPYTvlOQ ```.scala import chisel3._ import chisel3.experimental._ import firrtl.annotations.PresetAnnotation import chisel3.stage.ChiselStage class Foo extends...

Potentially. We would have to play around with this a little bit.

We have a feature request (from me) for FST support for treadle which would allow us to get FST from both treadle and Verilator: https://github.com/chipsalliance/treadle/issues/101

> Checking for the version string / FIRRTL in it would enable a trivial heuristic to differentiate the two. Great thinking. Wouldn't all older FIRRTL files start with `circuit`? Then...

> OTOH it's still inconsistent with the other verification ops Afaik, the Chisel frontend does not actually use the message field for `assert` and `assume`. Instead a `printf` is generated...

> So I guess I am saying I am in favor of keeping in the spec as a string that can be lowered into a comment, unless optional name allows...