Add support for the `PresetRegAnnotation`

[ekiwi]

This annotation is emitted by the PropagatePresetAnnotations pass from firrtl and should result in the annotated register starting at its init value at the start of simulation. It would be great if treadle could automatically detect this annotation and use it similar to how memory initialization is already supported.

[chick]

@ekiwi can you provide, or point me to, an example module and test?

[ekiwi]

Here is an example where you would expect the output to always be 123 and never 0: https://scastie.scala-lang.org/TlYbM54hSLOShAxPYTvlOQ

import chisel3._
import chisel3.experimental._
import firrtl.annotations.PresetAnnotation
import chisel3.stage.ChiselStage

class Foo extends MultiIOModule with RequireAsyncReset {
  annotate(new ChiselAnnotation {
    override def toFirrtl = PresetAnnotation(reset.toTarget)
  })
  
  val out = IO(Output(UInt(8.W)))
  
  val r = RegInit(123.U(8.W))
  dontTouch(r)

  out := r
}

println(ChiselStage.emitVerilog(new Foo))