Edward Chen
Edward Chen
**Description** Replace references to onnxruntime 'master' with 'main' in Dockerfiles. **Motivation and Context** Fix some remaining references to 'master' after the branch got renamed. Addressed instances found with `git grep...
TensorProto has a segment member. From [here](https://github.com/onnx/onnx/blob/c2a8d5258a433c56a838b08c1b088e8da2dadf12/onnx/onnx.in.proto#L487): ``` // For very large tensors, we may want to store them in chunks, in which // case the following fields will specify...
### Description Make classes IKernelTypeStrResolver and IKernelLookup have protected destructors. https://github.com/isocpp/CppCoreGuidelines/blob/master/CppCoreGuidelines.md#c35-a-base-class-destructor-should-be-either-public-and-virtual-or-protected-and-non-virtual ### Motivation and Context Prevent destruction through base class pointer. Address static analysis warning.
**Description** Consolidate enabled/default kernel def type constraint types into enabled. **Motivation and Context** Clean up following #12791
**Description of the false positive** The alert is "Static function IsTypeProtoCompatible is unreachable". [Help for that alert](https://lgtm.com/rules/2152580467/) indicates that it is about an unused static function. However, that function is...
### Description In build_custom_android_package.py, add --docker_run_env option to set environment variables for 'docker run'. ### Motivation and Context Setting environment variables in the docker container may be useful. E.g., for...
### Description Move workspace size calculation functions to hardware-specific implementations. ### Motivation and Context The workspace usage may be hardware-specific. Moving away from a common workspace size calculation allows more...
### Description Update AArch64 SQNBitGemm CompInt8 kernels to process matrix in tiles. E.g., dividing the output into 2x2 tiles allows us to compute four elements of the output with one...
On my Windows ARM device, `cpuinfo_has_arm_i8mm()` returns false but the value of [`ID_AA64ISAR1_EL1`](https://developer.arm.com/documentation/ddi0601/2024-09/AArch64-Registers/ID-AA64ISAR1-EL1--AArch64-Instruction-Set-Attribute-Register-1) indicates that I8MM is supported. From a look at the code, I did not see where `cpuinfo_isa.i8mm`...
Background: On a Windows ARM system, I observed that `cpuinfo_has_arm_fp16_arith()` started to return false after upgrading to a more recent cpuinfo version. In #333, the initialization of `cpuinfo_isa.fp16arith` was updated...