dvusingh

Not able to get waveform using verilator (vcd file, fst file)

8

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hi, I am trying to generate waveform in Verilator...

how to change the start address of cva6

43

Hi, I am doing the verification of cva6. I want to know how start address is generating or assigned as per the linkers script inside verif/tests/. May I know how...

Purpose of AXI_BUS, axi_master_connect dependency with axi_switch_vif in uvm_testbench

8

Hi, I observed that in the **cva6_tb_wrapper.sv file**, 1. we are connecting axi_interface signal based on axi_switch_vif as done in below assign statement ****assign axi_ariane_resp.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready :...

How to Include apb_uart

3

Hi, We want to integrate the uart in cva6. We have integrated uart in cva6 the way it is shown in the ariane _peripherals.sv file. But we are not seeing...

Issue With AXI_DATA_WIDTH parameter overiding

2

Hi, I am using the cv32a6_imac_sv32_config_pkg.sv config file to run the benchmark median test. In that file when I tried to modify the AxiDataWidth from 64 bits to 128 bits...

assertion failed for bresp

2

Hi, I tried to run the benchmarck median test with cv32_imac_sv32 configurantion file. The test is finished sucessfully and all the instructions are matched.But in the log file I found...

CVA6 Pulp Platform issue

2

Hi, I am working on the cva6 verification. There I found that some of the rtl files present under the **cva6/vendor/pulp_platform/axi & cva6/vendor/pulp_platform/common_cells** are old in comparison to the **github...