dvusingh
dvusingh
I pulled the last commits done by Zbigniew. But still there is no vcd or fst file present in my veri-testharness_sim directory. Thanks
Hi @zchamski, I tried export TRACE_FAST=1 option and ran the smoke_tests.sh script. But still, I am not able to get the .vcd file in my log directory. Note: I have...
Hi @zchamski and @JeanRochCoulon, I installed the verilator-5.005 and tried running smoke_test, but again vcd file is not generated. I also tried with DV_SIMULATORS=vcs-uvm, for this also I am getting...
Issue resolved. Thanks
Hi, I ran few testcases, but I found that the axi_slave is always in active mode. Also, I found 1 more issue that relates: Passive mode of AXI agents does...
Hi, Any updates on the passive mode agent's issue. Thanks
Hi, I want to run my simulation with passive agents with SRAM support. I want to collaborate to resolve the bug in passive agent in uvm-testbench. Any inputs how I...
Hi @AEzzejjari , Thanks for the update. So, I have to change the --axi_active=no and the list of files from this link https://github.com/openhwgroup/core-v-verif/commit/c01247b17eac00217784ef65f00ecbc87fe4ddbe. Any other modifications required? Thanks
Hi @AEzzejjari , I took all the changes from the **Connect the new AXI agent with CVA6 #2182 commit.** Also added the --axi_active="no" in benchmark.sh file When I am running...
> The testbench setup the boot_address input port of the cva6. You have to change it. I tried to change every address of boot_addr , but still the error is...