Damien Pretet

Write channels need also to be fixed for the issue mentioned [here](https://github.com/dpretet/axi-crossbar/issues/20#issuecomment-2566334113)

Both [read](https://github.com/dpretet/axi-crossbar/blob/ordering/rtl/axicb_slv_switch_rd.sv) and [write](https://github.com/dpretet/axi-crossbar/blob/ordering/rtl/axicb_slv_switch_wr.sv) channels are now upgraded in slave switchs to better support the OoO completion over different masters. Now will add a fix for #20 to complete this...

All devs are done, ready to be merged and tagged.

Hello, I have the same problem than @andylin2004 and would be glad to keep GTKWave in my workflow If possible. Thanks @randomplum for the fix :) It works also on...

Hello, thanks for your interest for this IP :) Good to see somebody is exercising it with UVM. 1/ Do you mean you have a wrong BRESP value or the...

Hello, I took a look to the waveform and many things are incorrect. - srst is unused, but you don't tied them to 0. Read the [documentation](https://github.com/dpretet/axi-crossbar/blob/main/doc/architecture.md#reset) about clocks and...

Good news bro, have a good journey 😎

Hello, Yes it’s expected, but I know it’s not very compliant with AXI4. I implemented this behavior to save area. Moreover, it could cause an ordering problem if several requests...

Hello, Yes, FIFOs are used across the core as buffers for outstanding requests storage. If an interface and the switch core are synchronous, I use single clock FIFO, else I...

Hello, I'm finishing #9 to ensure a correct ordering rule management. I think it's the right time after that to fix the issue you found on the write completion sequence....