Daniel Schultz
Daniel Schultz
I just want to report some unused flip-flop registers. They got removed during elaboration and since they are never used, they could also be removed? We should discuss how to...
This IP to en-/decode a 8b10b sequence is ported from Verilog to SpinalHDL [1]. This implementation only uses gates and does not rely on look-up tables. 1: https://github.com/freecores/1000base-x/tree/master/rtl/verilog Not sure...
Add missing comma and remove whitespaces before and after the first and last element in array. Signed-off-by: Daniel Schultz
I recently tried to create a Register with a default Bool value like ``` val first = RegInit(False) ``` but accidentally used `Reg` intead of `RegInit`. It seems like SpinalHDL...
Hi @Dolu1990, I'm currently in the process of bringing up the JTAG interface on the VexRiscv silicon. After I switched the TDO and TDI signals I got the following error:...
I found the following warning in OpenROAD and it looks like the stdcell lib has a type included: https://github.com/IHP-GmbH/IHP-Open-PDK/blob/dceb7e6bd1a877182c3ba32c2e238be08368fa3f/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p50V_25C.lib#L27289 `Warning: Found unsupported expression 'SCE*SCD+SCE'*D' in pin attribute of cell 'sg13g2_sdfbbp_1'...
### Describe the bug OpenROAD can add metal fill correctly to the core area but is missing the area where the power ring and IO cells are located. See screenshots...
Picked @KrzysztofHerman update script and modified it slightly. Synced files afterwards with this script and added the bondpad manually. Should we remove metal fill here since KLayout is supposed to...
Add all IO related lib, lef, and gds files when 'HAS_IO_RING' is set to 1. Those files will be appended to the 'ADDITIONAL_x' variables. - [ ] blocked by #2084
Add filler macros from Daniel Arevalos and Krzysztof Herman. Also add a Python script to automatically fill a layout and save it. The following example will fill all layers and...