Daniel Schultz

Thanks! I mostly ported the Verilog code and extended it with tests. Well, the license is a good point. The source is licensed under LGPL and can't be moved to...

> I'm not a lawyer but we may be okay to use as this long as we keep the original LGPL headers on this class specifically. We already provide the...

@kleinai @Dolu1990 - I sent a mail to the Author on the 29th of June. His company mail does not exist anymore and he did not reply from the other...

My thoughts about the maintainer topic: Github provides a codeowner [1] file to define people for reviewing pull-requests, which will be automatically assigned. The syntax also allows limiting people to...

I can confirm this assertion failure. Additionally to the posted trace, I also had a `failed at time=0`. Issue is related to VexRiscv and not SpinalHDL: https://github.com/SpinalHDL/VexRiscv/blob/77e361e91e93b5d292f795106e6981f5897818e8/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala#L523

@piegamesde well, I do not run tests without wave generation. I'll remove this parameter and run some tests in a loop.

@piegamesde - I was able to see this failure in two loops with and without this parameter.

@piegamesde - How is your clock domain configured? If it's synchronous, you should simulate the clock during reset is asserted. I have already created a PR to remove the assertion...

@piegamesde - Ah yes, maybe it's worth trying to trigger the reset after some nanoseconds. Sometimes I miss the X values from Xilinx's simulator. These random values are nice, but...

@piegamesde Can you share some Verilog code? AFAIK the simulation dumps it somewhere. `simWorkspace` in my project.