dmukherj09

Hi, Thank you for such a wonderful work for memory simulations. I wanted to ask can you help me to figure out, which part of the source code to edit...

Memory Hierarchy After the Simulation

2

Whenever I connect any type of memory system (CramSim/DramSim3/SimpleMem) with a setup of cache hierarchy which is driven by either some generic test-cpu/prospero-trace-based/ariel-binary-based, after the simulation is complete, I don't...

No write traffic beyond L1

1

Hello, I was implementing a system with 4 prospero cores together with 4 private L1 caches, shared L2,L3 caches and a main memory. I modified some of the source codes...

Discrepancy between the address of the memory trace request

12

Hi, I'm trying to interface a ProsperoCPU with the CramSim DRAM simulator with some caches in the hierarchy. I'm providing a trace file to the prosperoCPU and the program is...

Explanation of the statout.csv metrics

4

Can someone help me in understanding or point me in the direction of the document where I can get the information on various metrics dumped by the SST? ComponentName|StatisticName|StatisticSubId|StatisticType|SimTime|Rank|Sum.u64|SumSQ.u64|Count.u64|Min.u64|Max.u64 **cpu...

Ariel Core CPU cannot connect to Shared Type elements

1

Hello, I'm trying to configure a system which has a 8 core Ariel CPU connected with a shared cache which is then connected to the memory. Since the Cache is...

Hello all, I was trying to find but couldn't find a good sample for a mesh connected nodes of shared memory. Can you please provide me some basic python driver...