No write traffic beyond L1

[dmukherj09]

Hello,

I was implementing a system with 4 prospero cores together with 4 private L1 caches, shared L2,L3 caches and a main memory.

I modified some of the source codes to also dump information when there's a request from CPU <--> L1 , L1 <-->L2 , L2 <--> L3 , L3 <--> Main Memory.

After running the code I found out that beyond L1, i.e. in L2, L3.... there is no write requests which looked strange. So I went through the logs and I found out.

For read operations -- If the data is not there in cache, the system will send the requests L1 --> L2 --> L3 --> main memory and the data will come back in same order and then data request is fulfilled. Next time if the data is in the cache, it'll be read directly from the cache.

For write operations -- To write the data is also brought to L1 and then written into it, but if the data has to be kicked out, either that has to be written back to lower level of caches or to the main memory, but that was not happening. If the data is in L1 it is written there but when the block has to be kicked out it is not getting written back, which is wrong.

Does SST not propagate the data all the way back to the DRAM?

This is the comment which has the SDL file and other information https://github.com/sstsimulator/sst-elements/issues/2190#issuecomment-1685519969

[gvoskuilen]

Data should be getting written back to memory when it is evicted from L1. The block is marked as written in the cache and initiates a PutM request (writeback/modified) when the eviction occurs. Are you seeing these events occur? PutS - writeback/clean (only updates coherence state, for noninclusive caches, may also cache the block locally) PutE - writeback/clean from the owner of the block PutX - writeback exclusive ownership only, retain a copy of the block, not all coherence protocols use this PutM - writeback/dirty, a write to a lower level cache or memory