djsftree

Thanks Michael. I currently use a RV32IM core from https://github.com/SpinalHDL/VexRiscv I'll see about updating this hardware description to add A. Might take a little while. :-)

Hi Michael, A target for RV32IMA / ilp32 / with MMU would be a most welcome addition. Several IOT devices in development are using this spec core. Alpine Linux would...

Updated SoC - so we have RV32IM with partial A - "LR / SC" https://github.com/SpinalHDL/VexRiscv/commits/master