Add arch config

[djsftree]

Hi!

Could you possibly add and check rv32im/ilp32 variant? Such as?

riscv32im) ARCH=riscv32 LINUX_ARCH=riscv WITHARCH=--with-arch=rv32im --with-abi=ilp32 ;;

Many thanks!

[michaeljclark]

I'd consider adding riscv32ima.

It has been decided that the UNIX/Linux platform ABIs will mandate the A extension.

The latest Linux port has removed kernel support for atomic emulation (the cmpxchg syscall).

So A is now mandatory for the musl-riscv port given the Linux has removed the syscall.

Here is the commit that makes musl-riscv depend on A:

• https://github.com/rv8-io/musl-riscv/commit/7d34a4186e50af7528980d881562fba73f1b4ba2

[djsftree]

Thanks Michael. I currently use a RV32IM core from https://github.com/SpinalHDL/VexRiscv I'll see about updating this hardware description to add A. Might take a little while. :-)

[michaeljclark]

No worries. You could perhaps make a branch of musl-libc and revert the atomics commit mentioned above but you would also need to apply a patch to linux-kernel.

Currently musl-libc only depends on LR/SC (LR.W and SC.W on RV32 and LR.W, LR.D, SC.W and SC.D on RV64 e.g. int and pointer sizes which are equal on RV32).

I am not sure which atomic instructions linux-kernel depends on. It may use other AMOs in its spinlocks however these could be compiled out for non-SMP kernels. Userspace, on the other hand, needs to use LR/SC (or a syscall in earlier versions that supported A-less ABIs) as userspace can be pre-empted. In the case when userspace code is pre-empted by interrupts or the scheduler, the SC will fail accordingly.

The issue that is being avoided is a proliferation of ABIs on the Linux platform that has hurt other architectures. In the embedded case, people often customise code so that is not so much of an issue if you want to roll a version of the code without A, however, for Linux distributors, they don't want to deal with 'n' different ABIs. 2 is enough. e.g. 32-bit and 64-bit.

For Linux, it's likely that RV32GC (ilp32d) and RV64GC (lp64d) will be the standard ABIs.

[djsftree]

Hi Michael,

A target for RV32IMA / ilp32 / with MMU would be a most welcome addition. Several IOT devices in development are using this spec core. Alpine Linux would be an interesting experiment to try and compile and boot in rv8.

[djsftree]

Updated SoC - so we have RV32IM with partial A - "LR / SC" https://github.com/SpinalHDL/VexRiscv/commits/master