Dinesh Annayya

Results 25 comments of Dinesh Annayya

I don't know how to validate the reproducible locally . Design wise, I have done good amount of changes in this Pinmux block The flow gone through fine with set...

When run locally, I am getting different error, But still see a segmentation fault. Cell sky130_fd_sc_hd__mux2_1 couldn't be read Cell sky130_fd_sc_hd__mux2_1 couldn't be read Cell sky130_fd_sc_hd__mux2_1 couldn't be read Cell...

I feel issue is script is trying to fix hold based on margin in output of the cell. If the output of cell has two path, One have Hold violation...

@vijayank88 My Don't cell list is set ::env(DONT_USE_CELLS) {sky130_fd_sc_hd__a2111oi_0 sky130_fd_sc_hd__a21boi_0 sky130_fd_sc_hd__and2_0 sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__clkdlybuf4s15_1 sky130_fd_sc_hd__clkdlybuf4s18_1 sky130_fd_sc_hd__fa_4 sky130_fd_sc_hd__lpflow_bleeder_1 sky130_fd_sc_hd__lpflow_clkbufkapwr_1 sky130_fd_sc_hd__lpflow_clkbufkapwr_16 sky130_fd_sc_hd__lpflow_clkbufkapwr_2 sky130_fd_sc_hd__lpflow_clkbufkapwr_4 sky130_fd_sc_hd__lpflow_clkbufkapwr_8 sky130_fd_sc_hd__lpflow_clkinvkapwr_1 sky130_fd_sc_hd__lpflow_clkinvkapwr_16 sky130_fd_sc_hd__lpflow_clkinvkapwr_2 sky130_fd_sc_hd__lpflow_clkinvkapwr_4 sky130_fd_sc_hd__lpflow_clkinvkapwr_8 sky130_fd_sc_hd__lpflow_decapkapwr_12 sky130_fd_sc_hd__lpflow_decapkapwr_3 sky130_fd_sc_hd__lpflow_decapkapwr_4 sky130_fd_sc_hd__lpflow_decapkapwr_6...

Q.1: Have you received and tested the RISCDUINO? RISCDUINO project successfully got a tape-out slot efabless in MPW-3/MPW-4/MPW-5/MPW-6 Shuttle. Even though tape-out was done long back,still efabless yet to deliver...

@Aman-ECE Sorry busy with other technical work. A1. currently I have verified only in Ubuntu, I have moved this issue as bug. you can also contribute fix this issue as...

Hi RT Edward I feel there is some issue in the LVS logic, it sometimes shows there is mismatch in Pin Difference between RTL and Spice netlist. Here is a...

Tried one more experimenting with removing 2 un-used input. Still LVS fails here is failure looks Subcircuit pins: Circuit 1: spim_top |Circuit 2: spim_top -------------------------------------------|------------------------------------------- spi_debug[18] |(no matching pin) spi_debug[19]...

From my netlist review, I see these failing pins are having multiple fan-in/fan-out. Is it possible to add additional debug message on which are the different net connected to these...

I mean, last working netgen version for this example is checkout: 7ee50a3f8fc41dffad74adec7d32a691586351cf