David Biancolin

Results 44 issues of David Biancolin

**Impact**: other **Tell us about your environment:** CI: 2.31 (Dev clones fine) Manager: git version 2.24.2 (Dev clones fine) Mill: git version 2.17.1 (fails to resolve reference gemmini-rocc-tests) Weirdo machine:...

bug

This does not actually affect CI performance but makes it materially harder to debug. #### Related PRs / Issues #### UI / API Impact #### Verilog / AGFI Compatibility ###...

changelog:omit
ci:fpga-deploy

Not a great solution, but it'll have to do for now.

This to support black box references to Xilinx IP in the Platform Shims without providing an implementation. #### Related PRs / Issues #### UI / API Impact No change. ####...

changelog:changed

It appears that a some version between after L-2016.06-SP2-4_Full64 and M-2017.03-SP2_Full64, VCS started clobbering older allocations to the heap made by the driver (we enter through the driver before switching...

This has happened a couple times. There is likely some non-deterministic behavior in the test that requires investigation. See: https://github.com/firesim/firesim/runs/7529695382?check_suite_focus=true#step:3:2102

This should make it more clear what files are used where, allowing me to clean up some of the `replace-rtl` logic (we can drop per-platform junk), and easing integration into...

changelog:added

The current tasks are still manual and are candidates for automation. Please add to this list as necessary. Common: - [ ] Update Changelog. - [ ] Mint the release...

[This is not RTL changing] With the current parameterization (generation-time configuration) of FASED, to get the full 4MB capacity you need to use 128B lines at runtime. I'm seeing anomalous...

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