Dave Keeshan
Dave Keeshan
@mmospanenko Can you post an example of your `docker-compose.yml`? When you say external, do you mean available to the world via a domain name? I have this working internally. (Please...
verible version: [76cc3fad49a10c0bb69c519e71ea6965e6dd121c](https://github.com/chipsalliance/verible/commit/76cc3fad49a10c0bb69c519e71ea6965e6dd121c) I see this issue in code where the io is controlled by an `ifdef`, usually seen when added debug interfaces: ```verilog module core ( output aresetn ,...
What simulator are you using? I have noticed ghdl has problems with things more than 32 bits
I see this has been brought up in #64
Fixed in this PR: #3
bump Reviewing old pull request, this is still outstanding, this merge request should go through, python 3.12 could be added too
I got this working on the released verison of cocotb, 1.9.2. However with the next release, 2.0, there are some changes on how indexing of an vector occur, [subscriptable signals...
@spetca I forgot I had actually looked at this, also icarus versus xcelium, but to my eye they looked the same: ``` 0.00ns INFO cocotb.regression running test_array (1/1) 0.00ns DEBUG...
@amykyta3 @darsor I have rewritten virtually all the tests from `regblock` into cocotb for my project `etana`. Part of my verification flow is that my tests still work on the...
> > * It could be leveraged by the downstream VHDL exporter. Right now that exporter uses the same Systemverilog testbenches and auto-generates a test adapter between SV and VHDL....