Dave Keeshan

@mmospanenko Can you post an example of your `docker-compose.yml`? When you say external, do you mean available to the world via a domain name? I have this working internally. (Please...

verible version: [76cc3fad49a10c0bb69c519e71ea6965e6dd121c](https://github.com/chipsalliance/verible/commit/76cc3fad49a10c0bb69c519e71ea6965e6dd121c) I see this issue in code where the io is controlled by an `ifdef`, usually seen when added debug interfaces: ```verilog module core ( output aresetn ,...

What simulator are you using? I have noticed ghdl has problems with things more than 32 bits

I see this has been brought up in #64

Fixed in this PR: #3

bump Reviewing old pull request, this is still outstanding, this merge request should go through, python 3.12 could be added too