Naoya Hatta
Naoya Hatta
The table with `` tag becomes broken by translation. * Source ```markdown | Ferris | Meaning | | ---------------------------------------------------------------------------------------------------------------- | ------------------------------------------------ | | | This code does not compile! |...
To reduce compilation time for a large project, build cache can be used like below: * Load build cache to tables (e.g. symbol_table) * Check which files are updated, and...
Now bit concatenation uses `{}`, which is the same as statement block group. It prevents that bit concatenation is placed at the left hand side in `always_comb`. ```systemverilog always_comb {...
This is an idea to construct the official package registry like https://crates.io. To reduce maintenance cost, some cloud services can be used. * GitHub: stores the actual package metadata and...
The detailed definition of SystemFunction is added by #1443. Now arity check for SystemFunction can be implemented.
`connect` operation is suitable to introduce in the feature list of veryl-lang.org and the book.
Now assignment in initial block is checked based on assign statement. So assignment through output port of function call is not checked. ```systemverilog initial { x = 1; // Error...
Veryl compiler relies on external `git` command for some features. https://github.com/GitoxideLabs/gitoxide, which is pure-Rust Git implementation, seems to have sufficient features now. So using gitoxide, dependency to `git` command can...
Now all symbol information is already gathered, clock / reset is identified syntactically, and expression evaluator is ready. So I think implementing Veryl native simulator is not so difficult. The...
If many enum item is listed, the enum namespace becomes too long. ```systemverilog let x: logic = inside a {EnumX::A, EnumX::B, EnumX::C, EnumX::D, EnumX::E, EnumX::F}; ``` So importing enum items...