Naoya Hatta

From ``` project.list.rb ``` To ``` project.list.rb - src - src.list.rb - module_a - module_a.list.rb - dependencies - dependencies.list.rb ```

``` a = 3:2'f7.25; ```

SystemVerilog don't allow variable forward reference. It causes distributed variable declarations which are included in the same group. ``` // Move the declaration to the top of code to avoid...

This is only suggestion. I'm a contributer of Japanese translation of RBE, and worked to merge Japanese translation into the official repository. I think merging into the official has some...

Closes #877

`std` is refered by many dependencies, and it is used for interoperation between libraries. So it should be imported by default and just once through a whole project. There are...

Generic parameter `S` should be added in https://std.veryl-lang.org/async_fifo.html.

Generic parameter doesn't have any constraint. So user of the defined generics don't know which value is acceptable as generic parameter. ```systemverilog module ModuleA { inst u: GenericModule:: ( };...

The waveforms described by wavedrom are probably able to be used as test patterns. If the test patterns are validated by `veryl test`, equivalence between RTL and waveform documentation will...