Mitch Bailey

'M' Property Error on Single PNP

2

netgen `1.5.264` A single pnp transistor is extracted without an `M` parameter. Matching to a single pnp transistor in the source spice with an `m` parameter causes a mismatch. Here’s...

Netlists created with ext2spice short resistor should be equivalent to those created without

1

https://github.com/RTimothyEdwards/magic/issues/262

netgen doesn't handle attributes correctly or escapes inside escapes.

2

`Netgen 1.5.253` Sky130 MPW-4 Slot-029 coriolis_test_soc_-_mpw4 1. `(* ... *)` denotes attributes in verilog that various tools can use as needed. In netgen, they should probably be treated as comments....

Uninitialized count in pnp device count comparison

9

Slot-002 of mpw-3. ``` Subcircuit summary: Circuit 1: WY_SY_ldo_v1 |Circuit 2: ldo_v1 ----------------------------------------------------------------------------------|---------------------------------------------------------------------------------- sky130_fd_pr__pfet_g5v0d10v5 (870->14) |sky130_fd_pr__pfet_g5v0d10v5 (870->14) sky130_fd_pr__res_xhigh_po (122->16) |sky130_fd_pr__res_xhigh_po (116->9) **Mismatch** sky130_fd_pr__nfet_g5v0d10v5 (70->11) |sky130_fd_pr__nfet_g5v0d10v5 (70->11) sky130_fd_pr__cap_mim_m3_1 (2) |sky130_fd_pr__cap_mim_m3_1 (2)...

Netgen `1.5.253` Here's the schematic and here are the comparison results ``` sky130_fd_pr__res_xhigh_po:4 vs. bgr_sym:1/sky130_fd_pr__res_xhigh_po:R5: w circuit1: 36.57 circuit2: 37.26 (delta=1.87%, cutoff=1%) Circuit 2 parallel/series network does not match Circuit...

netgen `1.5.253` When the layout and source have differing hierarchy, the parallel/series parameters resulting from merging devices sometimes do not match. For example, from the gf180mcu SRAM macro, the layout...

Altering port lists with duplicate ports causes incorrect connectivity

7

See https://github.com/RTimothyEdwards/magic/issues/232

If there are circuit instances but no circuit definition, netgen will warn of a black box match. However, if the spice circuit exists and is a stub with no devices,...

Scripts for gf180 klayout drc are being pulled into the sky130 pdk

1

From at least `e0f692f46654d6c7c99fc70a0c94a080dab53571`, `sky130B/libs.tech/klayout/drc/klayout_gds_drc_check.py` contains ``` klayout_sky130A_mr_drc_script_path = Path(__file__).parent.parent.parent / "tech-files/gf180mcuD_mr.drc" ``` Maybe this needs to be forwarded to the rule maintainer repo. Reported by Aquiles Viza [here](https://open-source-silicon.slack.com/archives/C016UL7AQ73/p1709011536488259). >Hi...

In the `sky130_fd_io` library, the `top_gpiov2` layout contains a cell, the `res250only_small`, that has resistor definition layers on li1 `67/15`, poly `66/13`, and met1 `68/15`, but no actual mask layers....